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am/fm 1chip tuner with pll S1A0903X01 1 introduction ? am : am rf mixer, am osc, am_if amp,am detector, agc, tuning led driver, osc buffer, if buffer ? fm : rf amp, fm rf mixer, fm osc, fm_if amp, quadrature detector, tuning led driver, osc buffer, if buffer ? mpx : pll, stereo deco der, stereo led, mpx vco self-adjustment ? dts : prescaler, am/fm programmable divider, am/fm if counter, lock detector, led controller ? microprocessor interface feature ? adopt new fcc ? am/fm 1 chip dts with pll ? mpx-vco self-adjustment ? programmable divider fm : 10 ? 160mhz am : 2 ? 40mhz 0.5 ? 10mhz ? if counter : 0.4 ? 12mhz ? reference frequency twelve selectable frequency 1, 3, 5, 9, 10, 3.125, 6.25, 12.5, 15, 25, 50, and 100khz (selectable crystal 75khz, 3.6mhz, 7.2mhz, 10.8mhz choice) ? built-in transistor for forming an active low-pass filter ? package : 44 qfp/48 lqfp ordering information device package supply voltage operating tempeature S1A0903X01-q0r0 44-qfp-1010b 2 to 7v -20 ? +75 c S1A0903X01-e0r0 48-lqfp-0707an 44-qfp-1010b
S1A0903X01 am/fm 1c hip tuner with pll 2 block diagram 44-qfp lout rout tunled stled vssa aout ain pd vssx xout xin mixout amlowcut gnd_rf fmrfin amrfin fmrfout vcc_rf amosc vdda fmosc vcdc io[20:0] if[18:0] r[3:0] n[3:0] n[16:4] ul[1:0] xs[1:0] gt[1:0] test[1:0] dz[1:0] dlc doc[1:0] ifcs vreg test3 nc vdd test2 test1 vssd ce di cl do pd[6:0] mute ifs[1:0] most tunledc amifin vcc agccap fmifin detout gnd mpxin lpf1 lpf2 lpf3 fmquad 34 35 36 37 38 39 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 a a am det agc fm det level det fm mix am mix a a am osc b fm osc 1/2 b b b hys led control if counter vco mpx vco control pilot det phase det f/f f/f f/f f/f decoder led drv led drv a prescaler main counter swallow counter pfd doc[1:0] test[1:0] dlc tunledc most os[1:0] xs[1:0] r[3:0] ifcs mutec mute ifs[1:0] gt[1:0] dz[1:0] ul[1:0] n[15:0] data shift register charge pump lock detect ref divider test control serial interface
am/fm 1chip tuner with pll S1A0903X01 3 block diagram 48-lqfp lout rout tunled stled vssa aout ain pd vssx xout xin mixout amlowcut gnd_rf fmrfin amrfin fmrfout vcc_rf amosc vdda fmosc vcdc io[20:0] if[18:0] r[3:0] n[3:0] n[16:4] ul[1:0] xs[1:0] gt[1:0] test[1:0] dz[1:0] dlc doc[1:0] ifcs vreg test3 nc vdd test2 test1 vssd ce di cl do pd[6:0] mute ifs[1:0] most tunledc amifin vcc agccap fmifin detout gnd mpxin lpf1 lpf2 lpf3 fmquad 37 38 39 40 42 43 44 45 46 47 48 1 2 3 4 5 6 7 8 10 11 12 13 14 15 16 17 19 20 21 22 23 24 25 26 27 28 29 30 31 32 34 35 36 a a am det agc fm det level det fm mix am mix a a am osc b fm osc 1/2 b b b hys led control if counter vco mpx vco control pilot det phase det f/f f/f f/f f/f decoder led drv led drv a prescaler main counter swallow counter pfd doc[1:0] test[1:0] dlc tunledc most os[1:0] xs[1:0] r[3:0] ifcs mutec mute ifs[1:0] gt[1:0] dz[1:0] ul[1:0] n[15:0] data shift register charge pump lock detect ref divider test control serial interface 41 nc 9 nc 18 nc 33 nc
S1A0903X01 am/fm 1c hip tuner with pll 4 pin description pin configuration pin no. symbol in/out function 44-qfp 48-lqfp 1 1 lout o stereo left channel output 2 2 rout o stereo right channel output 3 3 tunled o tuning led 4 4 stled o stereo led 5 5 vssa - ground 6 6 aout o connections for the tr. used for the pll active lpf. 7 7 ain i 8 8 pd o pll charge pump output 9 10 vssx - crystal gnd 10 11 xout i crystal oscillator element connection 11 12 xin o (75khz, 3.6mhz, 7.2mhz, 10.8mhz) 12 13 do o serial data output to the microprocessor 13 14 cl i clock used for data synchronization for serial data input(di) and serial data output(do) 14 15 di i serial data input from the microprocessor 15 16 ce i chip enable for serial i/o 16 18 vssd - ground 17 19 test1 i/o only for test 18 20 test2 i/o 19 21 test3 o 20 22 vdd - regulator voltage input 21 23 vreg - regulator voltage output 22 24 nc - no connection * 48-lqfp: 9, 17 pin nc
am/fm 1chip tuner with pll S1A0903X01 5 pin no. symbol in/out function 44-qfp 48-lqfp 23 25 vcdc - vcc ripple rejection cap. 24 26 fmosc i fm oscillator input 25 27 vdda - power 26 28 amosc i am oscillator input 27 29 vcc_rf - rf-power 28 30 fmrfout o fm rf output 29 31 amrfin i am rf input 30 32 fmrfin i fm rf input 31 34 gnd_rf - rf-ground 32 35 amlowcut - am lowcut cap. 33 36 mixout o am/fm mix output 34 37 agccap - agc cap. 35 38 amifin i am if input 36 39 fmifin i fm if input 37 40 vcc - power 38 42 lpf1 - connection for the phase detector and the vco lpf 39 43 gnd - ground 40 44 mpxin i mpx input 41 45 detout o am/fm detect output 42 46 lpf2 - connection for the vco lpf 43 47 lpf3 - connection for the pilot detector and the phase detector lpf 44 48 fmquad - connection for the fm quad detector resonator * 48-lqfp: 33, 41 pin nc
S1A0903X01 am/fm 1c hip tuner with pll 6 pin description analog block i/o pin (terminal voltage : typical terminal voltage at no signal with test circuit, vcc = 3v, ta = 25 c) pin no. pin name internal circuit (standard 44-qfp device) terminal( typ.) voltage (v) 44-qfp 48-lqfp am fm 1 2 1 2 lout rout vcc gnd 37 39 1/2 1.1 1.1 3 4 3 4 tunled stled gnd vcc 37 3/4 39 - - 5 5 vssa 6 7 6 7 aout ain vssa vcc 37 7 5 6 - - - -
am/fm 1chip tuner with pll S1A0903X01 7 pin no. pin name internal circuit (standard 44-qfp device) terminal( typ.) voltage (v) 44-qfp 48-lqfp am fm 8 8 pd vdd vssa 20 8 5 - - 9 ? 20 10 ? 22 cf. digital block i/o pin 21 23 vreg gnd vdda 25 21 39 1.8 1.8 22 24 nc - - 23 25 vcccap gnd vcc 37 23 39 2.85 3.0 24 26 fmosc vcc_rf gnd 27 24 39 3.0 3.0
S1A0903X01 am/fm 1c hip tuner with pll 8 pin no. pin name internal circuit (standard 44-qfp device) terminal( typ.) voltage (v) 44-qfp 48-lqfp am fm 25 27 vdda - 3.0 3.0 26 28 amosc vcc gnd 37 39 26 3.0 3.0 27 29 vcc_rf - 3.0 3.0 28 30 30 32 fmrfout fmrfin gnd_rf vcc_rf vcc 37 27 28 30 31 3.0 0 3.0 0.8 29 31 amrfin vcc_rf gnd_rf 27 29 31 3.0 3.0 30 32 fmrfin cf. pin28 31 34 gnd_rf - 0 0
am/fm 1chip tuner with pll S1A0903X01 9 pin no. pin name internal circuit (standard 44-qfp device) terminal( typ.) voltage (v) 44-qfp 48-lqfp am fm 32 35 amlowcut vcc gnd 37 39 32 1.7 - 33 36 mixout vcc_rf fm mix gnd am mix gnd_rf vcc 27 36 33 39 31 3.0 2.9 34 37 agccap vcc gnd 37 39 34 - -
S1A0903X01 am/fm 1c hip tuner with pll 10 pin no. pin name internal circuit (standard 44-qfp device) terminal( typ.) voltage (v) 44-qfp 48-lqfp am fm 35 38 amifin vcc gnd 37 35 39 3.0 3.0 36 39 fmifin vcc gnd 37 36 39 3.0 3.0 37 40 vcc - 3.0 3.0 38 42 lpf1 cf. pin42 2.2 2.2 39 43 gnd - 0 0 40 44 mpxin gnd vcc 37 40 39 0.8 0.8
am/fm 1chip tuner with pll S1A0903X01 11 pin no. pin name internal circuit (standard 44-qfp device) terminal( typ.) voltage (v) 44-qfp 48-lqfp am fm 41 45 detout vcc gnd am fm 37 39 41 1.0 1.0 38 42 42 46 lpf1 lpf2 gnd vcc gnd vcc 37 38 39 37 39 42 2.2 2.2
S1A0903X01 am/fm 1c hip tuner with pll 12 pin no. pin name internal circuit (standard 44-qfp device) terminal( typ.) voltage (v) 44-qfp 48-lqfp am fm 43 47 lpf3 gnd vcc 37 43 39 2.2 2.2 44 48 fmquad gnd vcc 37 44 40 2.2 2.2
am/fm 1chip tuner with pll S1A0903X01 13 digital block i/o pin pin no. pin name internal circuit remark 44-qfp 48-lqfp (standard 44-qfp device) 9 10 vssx 10 11 11 12 xout xin vdda vdd vssx 25 20 11 10 19 12 13 do vssd 16 12 13 14 15 14 15 16 cl di ce 13/14/15 vssd 16 16 18 vssd 17 18 19 20 test1 test2 17/18 vdd vssd cdl 20 16 19 21 test3 vdd vssd cdl 20 19 16 20 22 vdd
S1A0903X01 am/fm 1c hip tuner with pll 14 input and output of serial data serial data format and timing ce cl di do internal data latching old new tlc tdh teh vih vil vih vil vih vil tcl tch tsu thd tes tdc figure. 1 serial data i/o format and timing parameter symbol conditions ratings unit min typ max data setup time t su di, cl 0.75 - - m s data hold time t hd di, cl 0.75 - - m s cock low level time t cl cl 0.75 - - m s clock high level time t ch cl 0.75 - - m s ce setup time t es ce, cl 0.75 - - m s ce hold time t eh ce, cl 0.75 - - m s data latch change time t lc - - 0.75 m s data output time t dc do, cl - - 0.35 m s t dh do, ce - - 0.35 m s
am/fm 1chip tuner with pll S1A0903X01 15 structure of di control data(serial data input) di di [ in1 mode ] [ in2 mode ] a1 i20 i19 i18 i17 i16 i3 i2 i1 ce cl di dsr data teh tlc tes thd tsu a0 old new i0 a1 a0 i20 i19 i18 i17 i16 i15 i14 i13 i12 i11 i10 i9 i8 i7 i6 i5 i4 i3 i2 i1 i0 0 1 os1 os0 n15 n14 n13 n12 n11 n10 n9 n8 n7 n6 n5 n4 n3 n2 n1 n0 ifcs mutec mute address osc select programmable divisor data (n1[3:0] : 4 bit , n2[15:4] : 12 bit) if cnt. start mute off control mute on/off a1 a0 i20 i19 i18 i17 i16 i15 i14 i13 i12 i11 i10 i9 i8 i7 i6 i5 i4 i3 i2 i1 i0 1 0 xs1 xs0 r3 r2 r1 r0 ifs1 ifs0 gt1 gt0 dz1 dz0 ul1 ul0 doc1 doc0 dlc tunledc most test1 test0 address x'tal select reference divider data if sensitivity control if measure time deadzone control unlock control do pin control deadlock clear tunled control mo/st control test data figure.2 serial data input timing and format
S1A0903X01 am/fm 1c hip tuner with pll 16 di control data no. control block/data function 1 programmable divider data os<1:0> n<15:0> select the input source fm : real divisor = 2 n am : real divisor = n n[3:0] are "don't care" in the case of amlf 2 if counter start data ifcs if counter start control data ifcs = 1 : start the if counter ifcs = 0 : reset the if counter after outmode sio, ifcs is automatically reset to 0 3 mute control data mutec, mute mute select/control data mutec = 0 : microprocessor set mute mute is automatically reset when tuning led is on whenever band is switched from am to fm, mute is automatically on until mpx vco free-running frequency self_adjustment is end 4 reference crystal data xs<1:0> crystal selection data os1 os0 lsb am/fm frequency range divisor(n) 1 0 n0 fm 10 ? 160mhz 256 ? 65535 0 1 n0 amhf 2 ? 40mhz 256 ? 65535 0 0 n4 amlf 0.5 ? 10mhz 4 ? 4096 mutec mute function 0 0 mute off self controlled 0 1 mute on 1 0 mute off microprocessor 1 1 mute on controlled xs1 xs0 crystal osc. 0 0 3.6mhz 0 1 75khz 1 0 7.2mhz 1 1 10.8mhz
am/fm 1chip tuner with pll S1A0903X01 17 no. control block/data function 5 reference frequency select data r<3:0> reference frequency selection pll stop mode programmable divider and if counter are stopped. charge pump's output is a high- impedance state. all stop mode all the frequency of dts control block is stopped control data are holded the previous state : no use 6 if sensitivity control data ifs<1:0> if sensitivity control r3 r2 r1 r0 reference frequency 3.6,7.2,10.8mhz 75khz 0 0 0 0 100 khz 0 0 0 1 50 khz 25 khz 0 0 1 0 25 khz 0 0 1 1 15 khz 15 khz 0 1 0 0 12.5 khz 12.5 khz 0 1 0 1 10 khz 0 1 1 0 9 khz 6.25 khz 0 1 1 1 6.25 khz 1 0 0 0 5 khz 5 khz 1 0 0 1 3.125 khz 3.125 khz 1 0 1 0 3 khz 3 khz 1 0 1 1 1 khz 1 khz 1 1 0 0 1 1 0 1 all stop 1 1 1 0 pll stop + x'tal osc. stop 1 1 1 1 pll stop ifs1 ifs0 sensitivity (am / fm) 0 0 0db / 0db 0 1 -4b / -5db 1 0 -8b / -10db 1 1 -12/ -16db
S1A0903X01 am/fm 1c hip tuner with pll 18 no. control block/data function 7 if counter control data gt<1:0> select if counter measurement time 8 dead zone control data dz<1:0> dead zone data on : both of nmos and pmos in charge pump turn on in the same time and dead zone is reduced off : each of nmos and pmos in charge pump turn mutual exclusively on 9 unlock state control data ul<1:0> decide the lock state with the width of phase error( y e) doc[1:0] = 2 : do pin is controlled with lock state ul[1:0] = 1 : width of y e set do pin low, else high gt1 gt0 measurement time (ms) 0 0 4 0 1 8 1 0 16 1 1 32 dz1 dz0 charge pump deadzone 0 0 on --0 0 1 on -0 1 0 off +0 1 1 off ++0 ul1 ul0 y e detection width do pin state 0 0 stopped hold the previous state 0 1 0 y e is directly out 1 0 0.55us y e is extended by 2ms 1 1 1.11us
am/fm 1chip tuner with pll S1A0903X01 19 no. control block/data function 10 do pin control data doc<1:0> do pin control data when ce is low, doc[1:0] controls do pin 11 deadlock clear control data dlc deadlock clear data dlc = 1 : the output of charge pump is forcibly set to low, which makes control voltage vcc and gets out of deadlock condition dlc = 0 : normal operation 12 tuning led control data tunledc led control data abobe condition is ifs[1:0] = 0 the point of turning tuning led on depends on the value of ifs[1:0] 13 mono, stereo control data most mono/stereo control most = 1 : set stereo mode most = 0 : set forcibly mono mode 14 test control data test<1:0> test data doc1 doc0 function 0 0 do pin open 0 1 1 0 dts pll = lock, do pin = open 1 1 if counting = end, do pin = low tunledc am fm 0 if 3 32db m => led on if 3 45db m => led on 1 if 3 32db m and within 450khz 5khz => led on if 3 45db m and within 10.7mhz 12.5khz => led on test1 test0 function 0 0 normal operation 0 1 test mode1 1 0 test mode2 1 1 test mode3
S1A0903X01 am/fm 1c hip tuner with pll 20 structure of do output data(serial test data output) do [ out mode ] di a1 o20 o18 o17 o16 o3 o2 o1 o0 thd tsu tdh tdc tdc teh tes o19 a0 ce cl di do a1 1 a0 1 o20 o19 o18 o17 o16 o15 o14 o13 o12 o11 o10 o9 o8 o7 o6 o5 o4 o3 o2 o1 o0 stid lock c18 c17 c16 c15 c14 c13 c12 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 c0 stereo indicate lock state if counter binary data figure.3 serial data output timing and format di output data no. control block/data function 1 stereo indication data stid stid = 1 : detect stereo stid = 0 : detect mono 2 pll locked state data lock lock = 1 : pll is lock lock = 0 : pll isn't lock 3 if counter binary data c18 ? c0 c18 : if counter value (msb) c0 : if counter value (lsb)
am/fm 1chip tuner with pll S1A0903X01 21 structure of test mode do output data(serial data output) do di [test mode0 ] [ test mode1,2,3] do di a1 o20 o18 o17 o16 o3 o2 o1 o0 thd tsu tdh tdc tdc teh tes o19 a0 ce cl di do os1 a1 a0 0 0 o20 o19 o18 o17 o16 o15 o14 o13 o12 o11 o10 o9 o8 o7 o6 o5 o4 o3 o2 o1 o0 os0 n15 n14 n13 n12 n11 n10 n9 n8 n7 n6 n5 n4 n3 n2 n1 n0 ifcs mutec mute a1 a0 0 0 o20 o19 o18 o17 o16 o15 o14 o13 o12 o11 o10 o9 o8 o7 o6 o5 o4 o3 o2 o1 o0 xs1 xs0 r3 r2 r1 r0 ifs1 ifs0 gt1 gt0 dz1 dz0 ul1 ul0 doc1 doc0 dlc tunledc most test1 test0 figure. 4 serial test data output timing and format do output data no. mode function 1 test mode0 when test[1:0]=0 in mode2 data, in1 data in data shift register is sent from do pin to microprocessor synchronously with the cl 2 test mode1,2,3 when test[1:0]=1,2,3 in mode2 data, in1 data in data shift register is sent from do pin to microprocessor synchronously with the cl
S1A0903X01 am/fm 1c hip tuner with pll 22 programmable divider structure serial interface ce cl a1 di do o20 o18 o17 o16 o3 o2 o1 o0 o19 a0 i20 i18 i17 i16 i3 i2 i1 i0 i19 a b figure.5 serial i/o timing a[1:0] mode di / do remarks 0 test data of in1(test[1:0]=0) or in2(test[1:0]=1,2,3) latched in dsr are transferred to serial interface, which data are transferred to micro- processor through do pin synchronized with the cl 1 in1 data i[20:0] from di pin are latched in in1 or in2 data shift register on b point. 2 in2 when os[1:0] in in1 mode is changed, n[16:0] is changed and r[3:0] is changed from pll stop mode, fr and fc counter are reset which make lock time of pll fixed. 3 out data of out mode latched in dsr are transferred on a point, which data transferred to microprocessor through do pin synchronized with the cl. ifcs bit is reset on b point, which makes micro-processor restart if counter ce doc1 doc0 outmode do pin state 0 0 0 x open 0 0 1 x open 0 1 0 x when lock bit in out mode is high, do pin holds the low state. 0 1 1 x when if counting is end, do pin holds the low state. 1 x x 0 open 1 x x 1 outmode data are transferred through do pin x : don't care
am/fm 1chip tuner with pll S1A0903X01 23 1/n block 1/n block is used for frequency down-scaling from am osc. or fm osc. to reference frequency fr and prescaler, swallow counter, main counter is used for a natural number dividing. fm osc/2 am osc xin [a] prescaler 1/16, 1/17 [b] [c] fp swallow counter main counter n[3:0] fc n[15:0] phase frequency detector f e r[3:0] reference divider 12 am = fr=fc=amosc/n fm = fr=fc=fmosc/2n n divider fr figure.6 1/n block diagram os1 os0 input frequency input frequency range a 1 0 fm / 2 5 ? 80 mhz b 0 1 amhf 2 ? 40 mhz c 0 0 amlf 0.5 ? 10 mhz n = (16 n2) + n1 = 17 n1 + 16 (n2 - n1) fc is derived from osc. divided by n, n2 is derived from n[16:4] and n1 is derived from n[3:0] n2 n1 17 17xn1 16 16x(n2-n1) counting number of m.c counting number of s.c divisor of prescaler counting number of m.c figure. 7 1/n counting method prescaler : operates on fm or amhf mode. swallow counter : counts down with n1 divisor and di vides fp by 17 on operation of swallow counter and divide by 16 until s.c reloads n1 at the end of fc 1 period. main counter : makes fc divided by n2 divisor from fp divided by 16 or 17 reference divider : makes fr divided by r[3:0] divisor from x'tal.
S1A0903X01 am/fm 1c hip tuner with pll 24 for fm with a step size of 50khz fm rf = 89.3mhz (if = 10.7mhz) fm vco = 100.0mhz reference clock(fr) = 50khz 100.0mhz(fm vco) ? 50khz( fr) ? 2 = 1000 ? 03e8(hex) o s 1 o s 0 n 1 5 n 1 4 n 1 3 n 1 2 n 1 1 n 1 0 n 9 n 8 n 7 n 6 n 5 n 4 n 3 n 2 n 1 n 0 i f c s m u t e c m u t e 1 0 0 0 0 0 0 0 1 1 1 1 1 0 1 0 0 0 x x x 0 3 e 8 x : don't care for fm with a step size of 50khz fm rf = 89.3mhz (if = 10.7mhz) fm vco = 100.0mhz reference clock(fr) = 50khz 100.0mhz(fm vco) ? 50khz( fr) ? 2 = 1000 ? 03e8(hex) for amhf with a step size of 5khz amhf rf = 21.75mhz (if + 450khz) am vco = 22.205mhz reference clock( fr) = 5khz 22.20mhz(am vco) ? 5khz( fr) = 4440 ? 1158(hex) o s 1 o s 0 n 1 5 n 1 4 n 1 3 n 1 2 n 1 1 n 1 0 n 9 n 8 n 7 n 6 n 5 n 4 n 3 n 2 n 1 n 0 i f c s m u t e c m u t e 0 1 0 0 0 1 0 0 0 1 0 1 0 1 1 0 0 0 x x x 1 1 5 8 x : don't care for amlf with a step size of 9khz amlf rf = 1161khz (if = 450khz) am vco = 1611khz reference clock( fr) = 9khz 1611khz(am vco) ? 9khz( fr) = 179 ? ob3(hex) o s 1 o s 0 n 1 5 n 1 4 n 1 3 n 1 2 n 1 1 n 1 0 n 9 n 8 n 7 n 6 n 5 n 4 n 3 n 2 n 1 n 0 i f c s m u t e c m u t e 0 0 0 0 0 0 1 0 1 1 0 0 1 1 x x x x x x x 0 b 3 x x : don't care
am/fm 1chip tuner with pll S1A0903X01 25 fc generated by first example of setting 'n' divisor n[15:0] = 03e8(hex) = 1000( dec) n1 = n[3:0] = 8 n2 = n[15:4] = 3e(hex) = 62( dec) fc is divided by 17 with the amount of n1 and divided by 16 with the amount of n2 - n1 in figure. 8. 1 2 3 4 5 6 8 7 9 10 11 12 13 14 15 16 17 osc/2 divided by 16 divided by 17 62 61 60 59 58 57 55 56 54 53 52 51 50 7 6 5 4 3 2 1 62 divided by 17 (n1) divided by 16 (n2 - n1) fp fc 0 61 60 n figure. 8 generated fc by first example
S1A0903X01 am/fm 1c hip tuner with pll 26 phase frequency detector fc fc fc fr fr fr state1 state2 state3 a=v l b=v h a=v l b=v l a=v h b=v l figure. 9 pfd state diagram fc fr vdd vssa pd b a b a d c f e a b e f c d figure. 10 pfd scheme states are changed on rising edges of fr or fc in figure. 9(fr moving to higher states and fc moving to lower states) suppose the circuit is initially in state 1, then alternate rising edges on fr and fc will cycle between states 1 and 2. if fc is constantly falling behind fr in phase, as in the timing diagram(figure. 11 a point), then eventually there will be two fr rising edges without an intervening fc rising edge. this will take the circuit to state 3, and thereafter it will cycle between state 2 and state3. for phase difference of fc and fr is almost zero, the rising edges of fr and fc are coincident, and the pd remains in state 2 almost all the time z-state phase frequency detector is composed of 3-state pfd and two mos gates state 1 : make the frequency of fc slower. state 2 : hold the frequency of fc. state 3 : make the frequency of fc faster. state transition at rising edges of fr and fc rising edge of fr : cause current state to go high rising edge of fc : cause current state to go low
am/fm 1chip tuner with pll S1A0903X01 27 vfc vfr 1 2 2 1 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 1 state t t t t t a va vb vpd figure. 11 timing diagram (dz[1:0]=0) differences of deadzone (in figure. 10) dz[1] dz[0] mx2 path mx4 path pmos / nmos deadzone remarks 0 0 b a on/on --0 (1) 0 1 a b on/on -0 (2) 1 0 a c off/off +0 (3) 1 1 a d off/off ++0 (4) dz[1:0] = 0 mode : even though pll loop is locked, generate phase error pulse and phase error correction pulse which make deadzone reduced. dz[1:0] = 1 mode : same as dz[1:0] = 0 mode, but a width of phase error correction pulse is relatively narrower. dz[1:0] = 2 mode : generate only phase error pulse but phase error correction pulse. dz[1:0] = 3 mode : same as dz[1:0] = 2 mode, but a width of phase error pulse is relatively narrower. dz[1:0] = 0 or 1 ? excellent c/n characteristics ? sidebands may be created by reference frequency leakage ? sidebands may be created by low-frequency leakage due to the correction pulse envelope. dz[1:0] = 2 or 3 ? pll loop stable deadzone pfd has to detect subtle phase error and makes phase error signal. there is a region that pfd doesn't make any phase error pulse due to the propagation delay or other factors, which is called deadzone. (detailed in ix. terminology)
S1A0903X01 am/fm 1c hip tuner with pll 28 old data new data ( os[1:0] or n[15:0] is changed ) ce dsr's data fc fr vpd a b z z z z z figure. 12 pfd and pd output relationship y error pulse is made from rising edge of fr and fc. if rising edge of fc is slower than that of fr, set vpd to low ? make the frequency of fc fast. (figure. 9 state1) if rising edge of fc is faster than that of fr, set vpd to high ? make the frequency of fc slow. (figure. 9 state3) a region with no y error makes vpd high impedance and hold the frequency of fc when data are changed in os[1:0], n[15:0] or changed in r[3:0] from pll stop mode. reset fc and fr counter(figure. 12 a) and change pfd in state 2 after new data is latched, accurate y error can be reflected on the first phase error(figure. 12 b) lock time can be estimated in advance depending on n[15:0] or os[1:0] is changed
am/fm 1chip tuner with pll S1A0903X01 29 locked state detection timing fr fc preset lock y error n(16) r(4) vco l.p.f 1/r 1/n lock detector phase frequency detector figure. 13 lock detection scheme getting lock state ul[1:0] lock state in serial data lock state on do pin remarks 0 hold the previous state 1 y e is out directly depending on sio timing y e is out directly 2 when y e is narrower than y e width more than 2ms, set lock 3 lock bit in serial data reflects lock state regardless of doc[1:0] do pin reflects lock state only when doc[1:0] is 2 ? lock : do pin = open , unlock : do pin = low
S1A0903X01 am/fm 1c hip tuner with pll 30 old data new data ( os[1:0] or n[15:0] is changed ) ce dsr's data vco frequency y error lock bit do pin lock unlock lock data in data out data out a b figure. 14 lock detection timing diagram lock bit in serial data lock bit in serial data shows unlock because vco frequency isn 't stable (figure. 14 a) ? wait at least several cycle and check lock again(figure. 14 b) needs several lock check in order to get more reliable result. lock state on do pin only when doc[1:0]=1 and ul[1:0] 1 0, lock state can be checked on do pin needs several lock check in order to get more reliable result.
am/fm 1chip tuner with pll S1A0903X01 31 if counter count if frequency during measurement time(gt[1:0]), start counting on ifcs setting high. if gt gt[1:0] if counter dsr c[18:0] ifcs 4/8/16/ 32ms lsb msb 0 - 18 figure. 15 if counter structure c[18:0] = f if gt : counted value (the number of pulse) gt1 gt0 measurement time(gt) gt1 gt0 measurement time(gt) 0 0 4 ms 1 0 16 ms 0 1 8 ms 1 1 32 ms gt ifcs measurement time if frequency figure. 16 if counter operation in figure. 16 when ifcs bit is zero, if counter is reset. on ifcs bit is turning to one, if counter starts to count if frequency during measurement time. then if counter holds the counted value. if doc[1:0] is 3, inform the micro- processor of the end of counting by means of setting do pin to be low. if c ounter is automatically reset after sending serial data to micro- processor and ready to count. if if frequency less than 45khz(fm : 1.07mhz) comes into if counter during first 100us of measurement time(gt[1:0]), inform micro-processor of the end of counting by means of setting do pin to be low in the case that doc[1:0] is 3, even though measurement time isn't passed . after measurement time(gt[1:0]) is passed, ifcs bit has to be held 1. unless ifcs bit is held to be one, counted if value is all re set to be 0. ifcs bit is automatically reset after micro-processor reads the counted if values.
S1A0903X01 am/fm 1c hip tuner with pll 32 mpx vco free-running-frequency self-adjusting controller fmsw pd[6:0] 1111110 tc 55.47ms 0.853ms b 1111101 xxxxxxx adjust mode c 1111111 0.853ms a figure. 17 mpx vco free-running adjustment timing diagram whenever band is switched to the fm mode, fm mpx vco free-running frequency will be adjusted between 302.5khz and 309.5khz using control code pd[6:0] a region : wait time for mpx vco to oscillate due to band switching. b region : measure mpx vco free-running fre quency and check whether free-running frequency is between 302.5khz ? 309.5khz or not. if mpx vco free-running frequency is between 302.5khz ? 309.5khz, hold the control code and end the adjusting. c region : reduce control code pd[6:0] into 1 step, make free-running frequency fast. if pd[6:0] is 1111111(bin), vco frequency will be minimum frequency and if pd[6:0] is 0000000(bin), vco frequency will be maximum frequency. in adjusting mpx vco free-running, mute will be set to one. the result of mpx vco free-running adjust is out through test1 pin, when test[1:0] is zero. test1 pin = 1 : operating vco free-running adjustment test1 pin = 0 : success adjusting vco free-running between 302.5khz ? 309.5khz test1 pin = 1.172khz/2 : 1.172khz/2 frequency is out when first adjustment cycle (maximum adjustment time : 164.7ms / 1 cycle) is failed. try to adjust vco free-running on and on, test1 pin is set to be zero when vco free-running frequency is between 302.5khz ? 309.5khz
am/fm 1chip tuner with pll S1A0903X01 33 test function test[1:0] test1 pin test2 pin test3 pin remarks in out in out out 0 - adjresult - - - (1) 1 - tfcout - tfrout tmpxvco (2) 2 tif - tledrstb - tifminmax (2) 3 tfcin - tfrin - - (2) adjresult : out mpx vco adjustment result 1 : on adjusting 0 : success in adjustment 1.172khz : 1st. adjustment cycle is failed, but adjusting 2nd, 3rd adjustment cycle. tfcout : fc frequency divided by n[16:0] tif : if frequency comes in through external source for test tfcin : fc frequency comes in through external source for test tledrstb : counter reset signal of tuning led control block comes in through external source for test tfrin : fr frequency comes in through external source for test tfrout : fr frequency divided by r[4:0] tmpxvco : mpx vco free-running frequency which is end of adjusting tifminmax : minimum and maximum of if frequency which is used to check tuning led operation test[1:0]=0 :inform the state of mpx vco free-running adjustment test[1:0]=1 : fc frequency for testing n divider block, fr frequency for testing x'tal divider block, mpx vco free-running frequency for testing mpx vco self adjusting block test[1:0]=2 : if frequency, reset signal of led control counter and if min. max value for testing led control block test[1:0]=3 : fc and fr frequency for testing pfd and lock detector (1) : if a[1:0] is zero, send the in1 mode data latched in dsr to micro- processor through do pin synchronized with falling edge of cl (2) : if a[1:0] is zero, send the in2 mode data latched in dsr to micro- processor through do pin synchronized with falling edge of cl
S1A0903X01 am/fm 1c hip tuner with pll 34 characteristics absolute maximum ratings parameter symbol ratings unit remarks supply voltage vs 10 v operating temperature top -20 ? +75 c storage temperature tstg -55 ? +150 c power dissipation pdmax 1800 mw temperature characteristics parameter symbol condition ratings unit remarks quiescent circuit current1(fm) d icc1 -20 ? +75 c 20 ua/ c quiescent circuit current2(am) d icc2 -20 ? +75 c 20 ua/ c electro_static discharge characteristics parameter condition pin no. ratings unit remarks human body model c = 100pf, r = 1.5k w all pins 2000 v machine model c = 200pf, r = 0 k w all pins 200 v cdm - all pins 500 v
am/fm 1chip tuner with pll S1A0903X01 35 electrical characteristics ( ta = 25 c, vcc = 3v. unless otherwise specified) fm f/e : f = 98mhz, fm = 1khz, d f = 22.5khz, am : f = 1mhz, fm = 1khz, 30% mod fm if : f = 10.7mhz, fm = 1khz, d f = 22.5khz, mpx : f = 1khz, l+r = 90%, p = 10%, vi = 150mv) parameter symbol condition ratings unit min. typ. max. supply voltage range vcc 2.0 - 7.0 v supply current iccq1 fm, vi = 0 6 13 18 ma iccq2 am, vi = 0 2.5 5 8 ma f/e input limiting voltage vi lim1 vo = -3db - 12 18 dbu local oscillation voltage vosc fosc = 108.7mhz 40 70 110 mv input limiting voltage vi lim2 vo = -3db 30 36 42 dbu detection output voltage vo det1 vi = 80dbu 60 80 110 mv s/n ratio s/n1 vi = 80dbu 55 65 - db fm if am depression ratio amr vi = 80dbu 40 50 - db thd thd1 vi = 80dbu - 0.2 1.0 % led turning on vl11 ifs[1:0] = 0 40 45 50 db m sensitivity vi12 ifs[1:0] = 1 46 51 56 db m vi13 ifs[1:0] = 2 52 57 62 db m vi14 ifs[1:0] = 3 58 63 68 db m voltage gain gv1 vi = 26dbu 30 55 - mv am rf detection output voltage vo det2 vi = 60dbu 60 85 110 mv led turning on vl21 ifs[1:0] = 0 22 27 32 db m vi22 ifs[1:0] = 1 28 33 38 db m vi23 ifs[1:0] = 2 32 37 42 db m vi24 ifs[1:0] = 3 36 41 46 db m am if s/n ratio s/n2 vi = 60dbu 32 42 - db thd thd2 vi = 60dbu - 1 2 %
S1A0903X01 am/fm 1c hip tuner with pll 36 parameter symbol condition ratings unit min. typ. max. maximum input voltage vimax stereo, thd = 3% 300 450 - mv voltage gain gv2 -5 -1 0.5 db channel balance cb mono -1.5 0 1.5 db thd1 thd3 mono - 0.2 1.0 % mpx thd2 thd4 stereo - 0.2 1.0 % separation 1 cs1 stereo, f=100hz 25 35 - db separation 2 cs2 stereo, f=1khz 25 35 - db separation 3 cs3 stereo, f=10khz 25 35 - db led turning on sensitivity vlon tunled=on, pilot only - 8 16 mv led turning off sensitivity vloff tunled = off, pilot only 1 6 - mv lamp hysteresis hy - 2 - mv capture range cr pilot only - 4 - % s/n ratio s/n3 mono 60 70 - db mute attenuation amute 65 75 - db input high level vih ce, di, cl 0.7vreg - - v voltage low level vil ce, di, cl 0 - 0.3vreg v output high level voh1 pd : lo=-1ma 0.7vreg - - v voltage low level vol1 pd : lo=1ma - - 0.3vreg v vol2 do : lo=5ma 0 - 0.3vreg v dts output voltage range vo aout 0 - 9 v internal feedback registance rf xin - 0.4 - m w input current iin1 ce, di, cl=vdd or gnd - - 5 m a iin2 xin=vdd or gnd 1.3 - 8 m a idd1 x'tal=10.8mhz, fm=130mhz - 2.5 6 ma supply current idd2 pll stop mode, x'tal=10.8mhz - 0.3 - ma idd3 pll stop mode, x'tal stop mode - - 10 m a
am/fm 1chip tuner with pll S1A0903X01 37 test circuit 44-qfp 34 35 36 37 38 39 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 ce di cl do micro- processor test in b.p.f 19khz brf 0.022uf 2k amrfin fmrfin 330 0.47uf ift1 1uf 450k 10.7m f2 330 vcc1 fmifin amifin 220uf 0.1uf 0.1 m f gnd 4.7uf 4.7uf detout mpxin 0..1uf 3.3uf 0.33 m f 10.7m f3 out 4.7uf 4.7uf 0.015uf 560 560 vcc2 10k 0.047 m f 1uf 2.2k 0.022 m f 10k x_sw 20pf 20pf test1 test2 test3 test out 0.1uf 10uf 2.2uf 68pf 4.7k vd1 l1 0.1uf 220uf 33k vd4 470pf t1 220uf 0.1uf 4.7k 68pf vd2 l2 2.7mh 10k S1A0903X01 f1 0.015uf
S1A0903X01 am/fm 1c hip tuner with pll 38 test circuit 48-lqfp 34 37 38 39 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 24 23 21 20 19 18 16 15 14 13 ce di cl do micro- processor test in b.p.f 19khz brf 0.022uf 2k amrfin fmrfin 330 0.47uf ift1 1uf 450k 10.7m f2 330 vcc1 fmifin amifin 220uf 0.1uf 0.1 m f gnd 4.7uf 4.7uf detout mpxin 0..1uf 3.3uf 0.33 m f 10.7m f3 out 4.7uf 4.7uf 0.015uf 560 560 vcc2 10k 0.047 m f 1uf 2.2k 0.022 m f 10k x_sw 20pf 20pf test1 test2 test3 test out 0.1uf 10uf 2.2uf 68pf 4.7k vd1 l1 0.1uf 220uf 33k vd4 470pf t1 220uf 0.1uf 4.7k 68pf vd2 l2 2.7mh 10k S1A0903X01 f1 0.015uf 12 17 22 25 35 36 45 46 47 48 nc
am/fm 1chip tuner with pll S1A0903X01 39 application circuit 44-qfp 34 35 36 37 38 39 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 ce di cl do micro- processor b.p.f fm antenna 330 0.47uf ift1 1uf 450k 10.7m f2 vcc1 220uf 0.1uf 0.1uf gnd 3.3uf 0.33uf 10.7m f3 560 560 vcc2 10k 0.047 m f 1uf 2.2k 0.022 m f 10k 20pf 20pf nc 0.1uf 10uf 2.2uf 68pf 4.7k vd1 l1 0.1uf 220uf 33k vd4 470pf t1 220uf 0.1uf 4.7k 68pf vd2 l2 10k S1A0903X01 f1 1000p 4.7u lout 0.015 m f 4.7uf rout 4.7uf 7.2m nc nc nc 20pf 10pf 12pf 33k am antenna vd3 22nf 0.015 m f b.p.f : gfm87 (korea sangshin electric co.ltd) f1 (450khz) : 450 bl(toko co.ltd) f2 (10.7mhz) : sfe 10.7ma5 (murata co.ltd) f3 (10.7mhz) : cdala10m7ga086-b0 (murata co.ltd)
S1A0903X01 am/fm 1c hip tuner with pll 40 application circuit 48-lqfp b.p.f : gfm87 (korea sangshin electric co.ltd) f1 (450khz) : 450 bl(toko co.ltd) f2 (10.7mhz) : sfe 10.7ma5 (murata co.ltd) f3 (10.7mhz) : cdala10m7ga086-b0 (murata co.ltd) 34 35 36 41 42 43 44 45 46 47 48 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 ce di cl do micro- processor b.p.f fm antenna 330 0.47uf ift1 1uf 450k 10.7m f2 vcc1 220uf 0.1uf 0.1uf gnd 3.3uf 0.33uf 10.7m f3 560 560 vcc2 10k 0.047 m f 1uf 2.2k 0.022 m f 10k 20pf 20pf nc 0.1uf 10uf 2.2uf 68pf 4.7k vd1 l1 0.1uf 220uf 33k vd4 470pf t1 220uf 0.1uf 4.7k 68pf vd2 l2 10k S1A0903X01 f1 1000p 4.7u lout 0.015 m f 4.7uf rout 4.7uf 7.2m nc nc nc 20pf 10pf 12pf 33k am antenna vd3 22nf 0.015 m f 12 nc nc nc 39 40 37 38 nc
am/fm 1chip tuner with pll S1A0903X01 41 0.5 1.0 2.0 4.0 8.0 16.0 40 50 60 70 80 90 100 thd (%) rf input level (dbu) am rf thd -rf level vcc=3v fin=1mhz fm=1khz,mod=30% 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 2 3 4 5 6 7 8 9 iccq2 (ma) vcc (v) am iccq - vcc vcc=3v fin=1mhz 0 25 50 75 100 125 150 175 200 225 250 0 10 20 30 40 50 60 70 80 90 voa1, voa2 (db) am modulation (%) am rf voa1,voa2 - modulation level vcc=3v fin=1mhz fm=1khz voa1 = rf in 26dbu voa2 = rf in 60dbu voa2 voa1 -60 -50 -40 -30 -20 -10 0 10 20 0 10 20 30 40 50 60 70 80 90 100 rf input level (dbu) am rf voa2,s/na -rf level vcc=3v fin=1mhz fm=1khz,mod=30% voa2, s/na (db) voa2 s/na am modulation (%) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0 10 20 30 40 50 60 70 80 90 thd (%) am rf thd - modulation level vcc=3v fin=1mhz fm=1khz rf in 60 dbu -5 -4 -3 -2 -1 0 1 2 3 4 5 3 4 5 6 7 8 9 voa2 (db) vcc (v) am voa2 - vcc vcc=3v fin=1mhz fm=1khz,mod=30% voa2=rf in 60dbu
S1A0903X01 am/fm 1c hip tuner with pll 42 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 thdf (%) rf input level (dbu) fm rf+if thdf-rf level vcc=3v fin=98mhz fm=1khz d f=22.5khz -20 0 20 30 40 50 60 70 80 90 100 -60 -50 -40 -30 -20 -10 0 10 vof,s/nf (db) rf input level (dbu) fm rf+if vof,s/nf - rf level vof s/nf vcc=3v fin=98mhz fm=1khz d f=22.5khz -20 -10 0 10 20 30 40 50 60 70 80 90 100 0.0 0.5 1.0 1.5 2.0 2.5 thdf (%) if input level (dbu) fm if thd - if level vcc=3v fin=10.7mhz fm=1khz d f=22.5khz -20 45 65 85 110 -60 -50 -40 -30 -20 -10 0 10 vof, s/nf (db) fm if vof,s/nf - if level vcc=3v fin=10.7mhz fm=1khz d f=22.5khz if input level (dbu) vof s/nf -20 20 40 60 80 100 fm icc - vcc 0 2 4 6 8 10 12 0 2 4 6 8 10 icc (ma) vcc (v)
am/fm 1chip tuner with pll S1A0903X01 43 3 2 1 4 5 6 f (mhz) 100 qo 80 turns 1-4 wire 7*(1/2) 0.45m/m kwang sung part no sp-2065 fm rf 3 2 1 4 5 6 f (mhz) 100 qo 80 turns 1-4 wire 6*(1/2) 0.45m/m kwang sung part no sp-2066 fm osc sp-2065 sp-2066 3 2 1 4 5 6 f (mhz) 796 qo 50 turns 1-3 wire 84 kwang sung part no ks50n-354 am osc ks50n-354 l (uh) 110 3 2 1 4 5 6 co (pf) 470 qo 40 turns 1-3 4-6 115 5 kwang sung part no ks50n-saa am ift (mix out) ks50-saa 1-3 f (mhz) 455
S1A0903X01 am/fm 1c hip tuner with pll 44 package dimensions 44-qfp 44-qfp-1010b #44 note : dimensions are in millimeters. 10.00 + 0.20 13.20 + 0.30 10.00 + 0.20 13.20 + 0.30 #1 0.35 + 0.10 - 0.05 0.80 0.10 max 0.80 + 0.20 0.05 min 2.05 + 0.10 2.30 max 0.15 + 0.10 - 0.05 0-8 0.15 max (1.00)
am/fm 1chip tuner with pll S1A0903X01 45 package dimensions 48-lqfp #48 7.00 bsc 9.00 bsc 7.00 bsc 9.00 bsc 0.08 max 0.09 - 2.20 0-7 note : dimensions are in millimeters. #1 0.20 + 0.07 - 0.03 0.50 bsc 0.08 max 0.60 + 0.15 0.10 + 0.05 1.40 + 0.05 1.60 max m
S1A0903X01 am/fm 1c hip tuner with pll 46 termonology deadzone pfd has to detect subtle phase error and makes phase error signal. there is a region that pfd doesn't make any phase error pulse due to the propagation delay or other factors, which is called deadzone. performance of pll frequency synthesizer depends on the width of deadzone the characteristic of pfd is not ideal a(figure. 18) but curved b(fig. 18) because pll frequency synthesizer operates on reference signal just like a lpf(low pass filter) the cause of deadzone is that pfd doesn't generate phase error signal even though there is a phase error between reference frequency and vco divided by n. in general deadzone has several nano seconds width. to implement a high s/n ratio system, the width of deadzone is as narrow as possible. but, rf leakage in mixer block comes into vco, which causes be a noise. y (ns) v a b deadzone figure. 18 pfd characteristic
am/fm 1chip tuner with pll S1A0903X01 47 application note 1. recommend using filter with 330 w i/o impedance as 10.7mhz if filter 2. output gain of rf mixer is fixed by both of 330 w register on pin33 and parallel register of input impedance on 10.7mhz if filter. thereafter to control output gain of mixer depends on changing load register on pin 34, which case both of input impedance of if filter and load register are recommended to have same impedance. 3. application of a input pin ce, di, cl depends on the output of micro-processor(figure. 19). input pin of ce, cl, di must be set to be vdd using r1 and r2 in the case of figure.19 . vreg 100k vreg r2 vdd r1 S1A0903X01 micom cl,di,ce (13,14,15) micom cl,di,ce (13,14,15) < a > < b > S1A0903X01 21 figure. 19 connection between sio and microprocessor 4. crystal can be selectable among 75khz, 3.6mhz, 7.2mhz, 10.8mhz. the connection must be the same as figure. 20 to share crystal for micro-processor xin micom S1A0903X01 11 figure. 20 connection x'tal for micro-processor
S1A0903X01 am/fm 1c hip tuner with pll 48 notes

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